1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly to a dynamic random access memory (DRAM) having a memory cell array of dynamic type memory cells formed of a MOS transistor for a transfer gate and a capacitor for data storage.
2. Description of the Related Art
FIG. 1 shows an equivalent circuit of a DRAM cell which is put to practical use at present.
This type of the DRAM cell is formed of a (insulating gate type) transistor Q for a transfer gate to be connected to a word line (WL) and a bit line (BL), and a capacitor C for data storage to be connected to the transistor Q.
For reading out data stored in the capacitor C, among electric charges stored in the capacitor C, the electric charge of a first capacitor electrode CP1 connected to the transistor Q contributes potential change to the bit line BL. Then, a bit line sense amplifier (not shown) sense-amplifies the potential difference between the potential of one bit line BL after the electric charge is moved and the potential of the other bit line which is paired with one bit line BL. In this case, among electric charges stored in the capacitor C, the electric charge of a second capacitor electrode CP2, which is opposite to the first capacitor electrode CP1, does not directly contribute the potential change to the bit line BL.
In sense-amplifying a signal read out from the DRAM cell by the bit line sense amplifier, it is possible to reduce read error of data by using larger potential difference between the bit lines.
For example, 1991 Symposium on VLSI ckts. pp. 59-60, May 30, 1991 "Cell-Plate Line Connecting Complementary Bit line (C3) Architecture for Battery Operating DRAMs" by M. ASAKURA et al discloses a DRAM using the electric charge of the second capacitor electrode (on one end of the data storage capacitor) which is opposite to the first capacitor electrode (on the other end of the data storage capacitor and connected to the transistor of the cell), so as to increase the potential change of the bit lines in reading out data from DRAM.
FIG. 2 is a circuit diagram showing a part of a memory cell array of the DRAM disclosed in the above reference.
The DRAM has a capacitor common line CPL to which the capacitor electrode on the other end of the capacitor C for the data storage of each memory cell MC of the same column in the memory cell array is connected. The common line CPL is structured so as to be selectively connected to the bit line BL or BBL of each of the paired complementary bit lines of the column. Then, in reading out data of the DRAM cell to one bit line BL, the common line CPL is connected to the other bit line BBL, thereby the potential of the bit line BBL is changed in a direction opposite to the direction of the potential change of the one bit line BL, and the potential difference, serving as an input of the bit line sense amplifier SA, between the bit line and the capacitor common line is increased.
However, in the circuit structure of FIG. 2, when the common line CPL is connected to the one bit line BBL, floating capacity Cb of the bit line BBL itself is added to floating capacity Cp of the common line CPL. In this case, the bit line capacity Cb is sufficiently large as compared with the capacitor capacity Cs of the DRAM cell. Normally, the bit line capacity Cb has the same order as the capacitor common line capacity Cp or a larger order than the capacitor common line capacity Cp. Due to this, the amount of the potential change of the common line CPL cannot be always sufficiently obtained.